Continuing progress in the semiconductor industry is leading to ever-smaller structures that have to be processed on the surface of a substrate, such as a silicon wafer. Presently, structures that are to be processed on the surface of a wafer are transferred to the wafer by photolithographic methods, i.e. by projecting the structures through a mask on the wafer surface. This is normally done using ultra-violet light that allows, due to its short wave length, the generation of small structures and can at the same time be used to activate material, such as photo resistive coatings of the wafer. The desire to further decrease size of the semiconductor structures thus leads to the problem of projecting structures of the size of hundreds of nanometers or possibly even of tens of nanometers to the wafer surface. The transfer of the desired structure from the mask to the surface of the wafer was continuously developed and an on-going decrease of structure size was accomplished in the past using different physical effects, such as decreasing the structure size using media of high refraction index in between the mask and the wafer. Nonetheless, the limit of the optical transfer processes seems to be nearly reached.
Several different approaches to further decrease the structure size in the future are discussed. Particularly attractive are so-called nano-imprinting techniques that achieve the application of the structures on the waver surface by a printing technique, comparable to a normal stamp. On the one hand, stamps of solid material, typically of metal such as nickel, can be applied to mechanically imprint a structure on the surface. On the other hand, one may use stamps of soft materials, such as PDMS (Polydimethylsiloxan), that can transfer Thiole to the surface of the wafer, which may prevent the surface from chemical etching. Using nano-imprinting techniques, structure sizes can easily go down to the nanometer scale, i.e. transistors with gate lengths in the 10 nm-regime become feasible.
Typically, the production of a semiconductor device comprises several consecutive steps of different processes, such as edging or photolithography, wherein each of the steps has to be precisely aligned with the preceding step to produce a functional semiconductor device. It may be noted that also the production of microscopic mechanical elements on substrates is a field of high commercial interest and shares the same demands on high alignment precision of consecutive production steps. It is evident that a transition to future structures, for example, by nano-imprinting, will further increase the accuracy demands of the alignment processes.
During the processing of a semiconductor device alignment of the semiconductor with respect to processing devices is normally required several times during the production. This is typically done using marks which are imprinted on the surface of the wafer A typical computer processor has only an active area of several hundreds of mm2, whereas a waver may be as big as 30 cm in diameter. That is only a small fraction of the wafer size is processed in a single photolithographic step and thus the complete wafer is processed by a sequence of consecutive photolithographic steps across the wafer surface. Once the complete wafer surface is processed, one proceeds to a next production step, transferring more structures on the wafer. That is, each wafer segment or process area (corresponding to the size of a single photolithographic step) has to be aligned with the processing unit in the next step of the process for guaranteeing a fully functional device.
This is normally done by marks surrounding the individual process areas and that allow for an adjustment of the process unit with respect to the process area before processing the wafer. Normally, the marks are detected and adjusted by optical methods that provide sufficient accuracy for the optical processing techniques currently available. For further proceeding technology, i.e. decreasing the structure sizes into the nanometer regime, the precision of these alignment procedures is insufficient.
One further problem of the marks surrounding the process areas is that these marks have to be transferred or refreshed after each single production step, since the marks themselves may be erased or falsified by certain process steps, such as sputtering or edging. Therefore, the marks themselves have to be transferred to each consecutive production step, which may yield accumulating errors during the production, decreasing the efficiency of correctly manufactured semiconductor devices on the wafer. Apart from these principle problems of the prior art, there are also technical problems, such as the space that is required for the prior art optical alignment systems. When using nano-imprinting methods for the production the very first production step can principally be performed without alignment. However, when it comes to consecutive production steps, alignment is still required even with higher accuracy, when using the nano-imprinting technique with its structure sizes in the nm-regime.
The space-problems (related to the space required for alignment systems close to the process units) tend to increase when going to nanometer-scales, since then, systems that are able to adjust on a nanometer scale are rather big (compared to the size of the device that has to be structured). In the case of nano-imprinting, an alignment system operating on a nanometer scale that is incorporated into the processing unit (stamp) is presently not feasible. An atomic force microscope is a high precision measurement tool, that is probing the surface of a material by a mechanical probe which has a tip of the size of essentially one atomic diameter (in the order of 10−10 nm). Although the tip itself and the needle having this tip, is normally rather small, the read-out is performed with an optical laser system that detects the tip movement by a change of the position of a reflected laser spot on an imaging device. To detect movements of several nanometers, the dimensions of the read-out system have to be rather big, thus making it infeasible to incorporate them into the process unit that stamps the surface of a wafer.
One further big disadvantage of the prior art method is that the alignment (adjustment) of the process unit with respect to the wafer and the processing itself is done in a sequential manner, i.e. one alignment step is preceding each processing step, which is putting limits to the overall efficiency of a production process using prior art alignment.
This is especially true. when either the processing or the adjustment is consuming much more time than its counterpart, which means that in the view of overall processing time for a single wafer, a lot of time is wasted awaiting the end of one particular process step.